FIG. 1 is a sectional view of the conventional memory device.
In general, the memory device has a cell area 10-2 and a peripheral area 10-1 which are separated from each other by a field oxidation layer 12.
A gate oxidation layer 13-1 and a gate 14-1 are provided on the peripheral area 10-1 of p type substrate 11, and n+ source/drain region 15-1 is formed near the surface of p type substrate 11 of both sides of the gate 14-1.
The source/drain region 15-1 is connected to a source/drain electrode 17-1 through a contact hole.
A gate oxidation layer 13-2 and a gate 14-2 are provided on the cell area 10-2 of p type substrate 11, and n+ source/drain region 15-2 is formed near the surface of p type substrate 11 of both sides of the gate 14-2.
The source/drain region 15-2 is connected to a source/drain electrode 17-2 through a contact hole.
The reference numeral 16 designates an insulating layer for an insulation between a source/drain electrode 17-1(17-2) and a gate 14-1(14-2) in the peripheral area 10-1(in the cell area 10-2).
It is seen from the above description that the gate oxide layer in the cell area 10-2 has the same thickness as that of the peripheral area 10-1.
Generally, the voltage of 3.3 V is applied to the gate 14-1 in the peripheral area 10-1 and 5.5 V(3.3 V+3 Vt) applied to the gate 14-2 in the cell area 10-2.
Particularly, in DRAM with memory capacities of 64M, very large area of about 0.1 cm2 (0.4.times.0.35.times.67.1.times.10.sup.6) within the cell area 10-2 is required for the gate 14-2 and the gate oxidation layer 13-2, and in comparison with said area, a smaller area within the peripheral area 10-1 is required for the gate 14-1 and the gate oxidation layer 13-1.
Though the device geometries are scaled to smaller dimensions below 100 angstrom, the occupied smaller area allows it to be ignored the defect which can be created during the procedure of the gate formation.
However, the reliability of the device is dependent on the cell area of larger area in which high voltage is applied, which results in the difficulty in fabricating the device with the scaling below 100 angstroms.
Also, in case that there are commonly formed the gate oxidation layers of the same thickness in the smaller peripheral area to which low voltage is applied and the larger cell area to which high voltage is applied, MOS transistor of the peripheral area exhibits the features of the reduced driving current and low-speed, and MOS transistor of the cell area has the feature of the reliability degradation.